This application claims priority under Title 35, United States Code, Section 119(a)-(d) of German application 101 34 178.4 filed Jul. 13, 2001, currently pending.
The invention relates to a semiconductor memory having a plurality of memory-cell arrays, a plurality of sense-amplifier areas and a plurality of driver areas on a semiconductor substrate of a first conductivity type, each of the multiple sense-amplifier areas and multiple driver areas containing at least one first well of the first conductivity type and/or at least one second well of a second conductivity type, and each first well of the driver areas being isolated from the semiconductor substrate by a buried horizontal layer of the second conductivity type.
In traditional semiconductor memories having a matrix-like layout of the memory-cell arrays, a driver area (segment driver) and a sense-amplifier area are arranged near each memory-cell array. In order to be able to drive each of the cells independently of the potential of the actual substrate of the semiconductor memory, the cells and their select transistors are isolated from the substrate. This is done by arranging each cell array and each area respectively in its own well. Each well occupies space on the surface of the semiconductor memory, however, so that the total area required for the memory increases.
The object of this invention is to create a semiconductor memory that requires less space.
This object is achieved by a semiconductor memory according to claim 1. Preferred embodiments of the invention are the subject of the dependent claims.
According to the invention, a well is not required for each separate cell array nor for each separate area, and instead of this the buried horizontal layer (cell-array well) extends under the driver areas and preferably the sense-amplifier areas. In order to avoid one of the wells of the driver transistors affecting the buried layer, the wells have a flatter design, indeed so flat that no electrical contact is made with the buried layer.
The development according to the invention of the semiconductor memory of this type is characterized in that the buried horizontal layer extends continuously beneath at least all the memory-cell arrays and the multiple driver areas of the semiconductor memory, and the second well is separated from the buried horizontal layer so that the second well is electrically isolated from the buried horizontal layer.
In particular, the buried horizontal layer extends continuously beneath all cells, including beneath the multiple sense-amplifier areas of the semiconductor memory.
In a preferred embodiment, transistors of the first conductivity type are arranged in the second well at the edge of the semiconductor memory.
In a preferred embodiment, at least one electrical circuit is arranged in the buried horizontal layer at the edge of the semiconductor memory, the electrical circuit, of which there is at least one, having a raised supply voltage or a reduced reference potential.
An advantage of the invention is that any increased production costs that might arise are more than compensated for by the gain in chip area.
Further features and advantages of the invention arise from the following description of exemplary embodiments with reference to the attached drawings.